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TDA7565
QUAD POWER AMPLIFIER WITH BUILT-IN VOLTAGE CONVERTER
PRODUCT PREVIEW
s s s s
DMOS POWER OUTPUT NON-SWITCHING HI-EFFICIENCY AMPLIFIER SWITCHING HIGH EFFICIENCY VOLTAGE CONVERTER HIGH OUTPUT POWER CAPABILITY 4x60W EIAJ/4 FULL I2C BUS DRIVING: - ST-BY - INDEPENDENT FRONT/REAR SOFT PLAY/MUTE - SELECTABLE GAIN 26dB - 12dB (FOR LOW NOISE LINE OUTPUT FUNCTION) - HIGH EFFICIENCY ENABLE/DISABLE - VOLTAGE CONVERTER ENABLE/DISABLE - REGULATED VOLTAGE SELECTION - SWITCHING FREQUENCY SELECTION HARDWARE MUTE FUNCTION FULL FAULT PROTECTION DC OFFSET DETECTION FOUR INDEPENDENT SHORT CIRCUIT PROTECTION CLIPPING DETECTOR WITH SELECTABLE THRESHOLD (1%/10%) VIA I2C BUS
MULTIPOWER BCD TECHNOLOGY
MOSFET OUTPUT POWER STAGE
s
FLEXIWATT27
ORDERING NUMBER: TDA7565
DESCRIPTION The TDA7565 is a new BCD technology QUAD BRIDGE type of car radio amplifier in Flexiwatt27 package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7565 has a very low distortion allowing a clear powerful sound. The built-in voltage converter control block assures a very high output power with an extremely low number of added components.The dissipated power under average listening condition is alligned to the conventional solutions (4x40W).
s s s s s
BLOCK DIAGRAM
VS MUTE CLK DATA VCC1 VCC2 CC GND
I2C BUS MUTE1 MUTE2
CLIP DETECTOR
VOLTAGE CONVERTER CONTROL
MG
VOLTAGE CONVERTER EXTERNAL CIRCUIT
IN RF
F OUT RF+ 12/26dB OUT RFR SHORT CIRCUIT PROTECTION OUT RR+ 12/26dB OUT RRF SHORT CIRCUIT PROTECTION OUT LF+ 12/26dB OUT LFR SHORT CIRCUIT PROTECTION OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION
IN RR
IN LF
IN LR
SVR
AC_GND
RF
RR
LF
LR
TAB
S_GND
D00AU1232A
PW_GND
September 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TDA7565
ABSOLUTE MAXIMUM RATINGS
Symbol Vopc OFF Vopc ON VS Vpeak VCK VDATA IO IO Ptot Tstg, Tj Parameter Operating Supply Voltage , converter OFF Operating Supply Voltage , converter ON DC Supply Voltage Peak Supply Voltage (for t = 50ms) CK pin Voltage Data Pin Voltage Output Peak Current (not repetitive t = 100s) Output Peak Current (repetitive f > 10Hz) Power Dissipation Tcase = 70C Storage and Junction Temperature Value 18 25 28 50 6 6 8 6 80 -55 to 150 Unit V V V V V V A A W C
THERMAL DATA
Symbol Rth j-case Description Thermal Resistance Junction-case Max. Value 1 Unit C/W
PIN CONNECTION
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MUTE DATA PW_GND RR OUT RRCK OUT RR+ VCC2 OUT RFPW_GND RF OUT RF+ AC_GND IN RF IN RR S_GND IN LR IN LF SVR OUT LF+ PW_GND LF OUT LFVCC1 OUT LR+ CC GND OUT LRPW_GND LR MG TAB
D00AU1233A
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TDA7565
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, VS = 13.5V; RL = 4; f = 1KHz; Voltage converter Disabled (VCOff); Tamb = 25C; unless otherwise specified.)
Symbol Parameter POWER AMPLIFIER Supply Voltage Range VS Total Quiescent Drain Current Id Id PO Total Quiescent Drain Current (VCon) Output Power (VCoff) V = 14.4V Output Power (VCon) V = 14.4V Total Harmonic Distortion EIAJ (VS = 13.7V) THD = 10% THD = 1% EIAJ (VS = 13.7V) THD = 10% THD = 1% PO = 1W to 12W; STDMODE HE MODE; PO = 1-2W HE MODE; PO = 4-12W PO = 1-12W, f = 10kHz f = 1KHz to 10KHz, RG = 600 Test Condition Min. 8 180 TBD 35 25 20 60 40 31 0.03 0.03 0.1 0.15 55 100 26 12 60 15 50 75 70 70 -100 6.5 1.5 60 Typ. Max. 18 300 Unit V mA mA W W W W W W % % % % dB K dB dB dB dB V V dB KHz dB 100 90 7 10 10 170 1 10 2 165 400 1.5 2.3 100 7.5 20 20 185 2 15 2.5 Mute & Play A dB mV V V/s ms ms C % % V C KHz V V
PO
THD
0.1
0.5 130 26.5 1 12.5 1 100 20
CT RIN GV1 GV1 GV2 GV2 EIN1 EIN2 SVR BW ASB ISB AM VOS VAM TON TOFF
Cross Talk Input Impedance Voltage Gain 1 Voltage Gain Match 1 Voltage Gain 2 Voltage Gain Match 2 Output Noise Voltage 1 Output Noise Voltage 2 Supply Voltage Rejection Power Bandwidth Stand-by Attenuation Stand-by Current Mute Attenuation Offset Voltage Min. Supply Voltage Threshold Slew Rate Turn on Delay Turn off Delay Thermal Foldback Junction Temperature Clip Det THD level Offset Detection Thermal Warning
50 60 25.5 -1 11.5 -1
Rg = 600; GV = 26dB filter 20Hz to 22kHz Rg = 600; GV = 26dB filter 20Hz to 12kHz f = 100Hz to 10kHz; Vr = 1Vpk; Rg = 600 (-3dB)
100
D2/D1 (IB1) 0 to 1 D2/D1 (IB1) 1 to 0 155 D0 (IB1) = 0 D0 (IB1) = 1 Power Amplifier = play AC Input = 0 0 5 1.5
CDTHD VO Thw I2C
BUS INTERFACE Clock Frequency fSCL VIL VIH Input Low Voltage Input High Voltage
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ELECTRICAL CHARACTERISTICS (continua) (Refer to the test circuit, VS = 13.5V; RL = 4; f = 1KHz; Voltage converter Disabled (VCOff); Tamb = 25C; unless otherwise specified.)
Symbol Parameter VMin(pin27) Mute in Threshold Voltage VMout(pin27) Mute out Threshold Voltage AM(pin 27) Mute Attenuation VOLTAGE CONVERTER Vcc1, Converter Output Voltage Vcc2 (VC = ON) VS = 14V D3 (IB2) = 0; D6 (IB2) = D3 (IB2) = 1; D6 (IB2) = D3 (IB2) = 0; D6 (IB2) = D3 (IB2) = 1; D6 (IB2) = D6 (IB1) = 0; D7 (IB1) = D6 (IB1) = 1; D7 (IB1) = D6 (IB1) = 0; D7 (IB1) = D6 (IB1) = 1; D7 (IB1) = Io = 250mA Io = 20mA Io = 200mA Io = 5mA Co = 1nF Co = 1nF Io = 5mA Test Condition Amp. Mute Min. 3.5 80 90 Typ. Max. 1.5 Unit V V
Fs
Voltage Converter Switching Frequency
0 0 1 1 0 0 1 1
15 16.5 17.5 18.5 100 150 260 400 1 10.5 10 TBD 20 50 0.5
V V V V kHz kHz kHz kHz V V V V ns ns V
Vmgl Vmgh Vmgclamp tf tr Vmgl (VCoff)
Mos Gate Output Low Voltage Mos Gate Output High Voltage Mos Gate Output Clamp Voltage Fall Time Rise Time Mos Gate Output Voltage with Voltage Converter Disabled
Figure 1. Demoboard Schematic
C10 2.2nF L1 100H C8 220nF R1 50 C9 10nF R4 3.3 1W IN RF Q1 R3 10 2 STP60NE06 C1 220nF 16 22 C2 220nF IN RR 15 23 26 7 21 5 18 OUT RF+ R5 10 1W VCC C12 100nF C13 10F
VS (Vbatt) C7 2200F
STPS30L40CT D1 DGND SCL SDA C11 3300F
20
OUT RFOUT RR+
TDA7565
24
OUT RROUT LF+
C3 220nF IN LF 12
10
8 C4 220nF IN LR 13 6
OUT LFOUT LR+
4 MUTE 27 11 C6 10F 17 C5 1F 14 9 3 19 25 1
OUT LR-
D00AU1224B
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TDA7565
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7565 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown by fig. 2, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown by fig. 3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 22). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock pulse. * Transmitter master (P) when it writes an address to the TDA7565 slave (TDA7565) when the P reads a data byte from TDA7565 ** Receiver slave (TDA7565) when the P writes an address to the TDA7565 master (P) when it reads a data byte from TDA7565 Figure 2. Data Validity on the I2C BUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 3.
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 4.
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
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TDA7565
SOFTWARE SPECIFICATIONS All the functions of the TDA7565 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from P to TDA7565) or read instruction (from TDA7565 to P).
D7 D6 D5 D4 D3 D2 D1 D0(R/W) Address bit Address bit Address bit Address bit Address bit Address bit Address bit Read/Write bit 0 = Write instruction 1 = read instruction
If R/W = 0, the P sends 2 "Instruction Bytes": IB1 and IB2. IB1
D7 D6 D5 D4 Sel Freq Switch 1 Sel Freq Switch 2 Offset Detection start (D5 = 1) Offset Detection stop (D5 = 0) (off) Front Channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) Rear Channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) Mute front channels (D2 = 0) Unmute front channels (D2 = 1) Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) CD 1% (D0 = 0) CD 10% (D0 = 1)
D3
D2 D1 D0
IB2
D7 D6 D5 D4 D3 D2 D1 Voltage Converter Enabled (D7 = 1) Voltage Converter Disabled (D7 = 0) Regulated voltage selection 1 Test Speed Stand-by on - Amplifier not working - (D4 = 0) Stand-by off - Amplifier working - (D4 = 1) Regulated voltage selection 0) To be forced to "Level 1" Right Channel Power amplifier working in standard mode (D1 = 0) Power amplifier working in HiEff mode(D1 = 1) Left Channel Power amplifier working in standard mode (D0 = 0) Power amplifier working in HiEff mode(D0 = 1)
D0
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TDA7565
DB1
D7 D6 D5 D4 D3 D2 D1 D0 Thermal Warning X X X X Offset (LF) Short Circuit Protection (CH1) X
DB2
D7 D6 D5 D4 D3 D2 D1 D0 Off Status X Clip Detector Output X X Offset (LR) Short Circuit Protection (CH2) X
DB3
D7 D6 D5 D4 D3 D2 D1 D0 St-By Status X X X X Offset (RF) Short Circuit Protection (CH3) X
DB4
D7 D6 D5 D4 D3 D2 D1 D0 X X X X X Offset (RR) Short Circuit Protection (CH4) X
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Examples of bytes sequence 1 - Turn-On of the power amplifier with 26dB gain, mute on, diagnostic defeat, HighEff mode, voltage converter disabled.
Start Address byte with D0 = 0 ACK IB1 XX00X000 ACK IB2 0XX1XX10 ACK STOP
2 - Turn-Off of the power amplifier
Start Address byte with D0 = 0 ACK IB1 XXXXXXXX ACK IB2 XXX0XXX0 ACK STOP
4 - Offset detection procedure start
Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 XXX1XXX0 ACK STOP
4 - Offset detection procedure stop and reading operation.
Start Address byte with D0 = 1 ACK DB1 STOP
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The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leackage current or humidity between pins. The delay from 3 to 4 can be selected by software, starting from T.B.D. ms
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mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019
DIM. A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3
MIN. 4.45 1.80 0.75 0.37 0.80 25.75 28.90
MAX. 4.65 2.00 1.05 0.42 0.57 1.20 26.25 29.30
MIN. 0.175 0.070 0.029 0.014 0.031 1.014 1.139
MAX. 0.183 0.079 0.041 0.016 0.022 0.047 1.033 1.153
OUTLINE AND MECHANICAL DATA
22.07 18.57 15.50 7.70
22.87 19.37 15.90 7.95
0.869 0.731 0.610 0.303
0.904 0.762 0.626 0.313
3.70 3.60
4.30 4.40
0.145 0.142
0.169 0.173
5 (Typ.) 3 (Typ.) 20 (Typ.) 45 (Typ.)
Flexiwatt27 (vertical)
(1): dam-bar protusion not included (2): molding protusion included
V C B V H H1 H3 H2 R3 R4 V1 R2 R L L1 A
V3
L4
O
L2
N
L3
V1
V2
R2 L5 G G1 F
R1 R1 R1 E
FLEX27ME
D
Pin 1
M
M1
7139011
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TDA7565
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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